The relentless progress of Moore’s Law has periodically inspired major innovations – both in hardware and software – at specific points in time to keep performance growth on pace with transistor density. Industry has reached another such point as it encounters intellectual and engineering challenges in the form of power dissipation, processor-memory performance gap, limits to instruction level parallelism, slower frequency growth, and rising non-recurring engineering costs. As a consequence, when we consider how the large number of transistors that will be supplied at future technology nodes will be used to sustain performance growth, there are some inevitable trends, including i) replication of cores, ii) the use of high volume custom accelerators due to the fact that these devices have small footprint and dramatically less power consumption for the performance gains they offer, and iii) innovations in memory hierarchies. The preceding collectively inspire the development of Hybrid Virtual Machines (HVM) for heterogeneous many-core platforms – large scale, heterogeneous systems comprised of single or shared ISA general purpose cores intermingled with customized heterogeneous cores – accelerators, and using diverse memory, cache and interconnect hierarchies. Such platforms will be seen both, in individual user as well as rack scale and multi-rack scale systems in order to keep up with the growing application demands.

These Hybrid Virtual Machines will run applications belonging to a wide spectrum comprising of high performance applications like scientific computing, biological simulations etc, enterprise applications like financial processing, data processing etc to client applications like gaming and image processing. Achieving performance guarantees for these applications under the constraints imposed by this workload variability, power, cost and heterogeneity then, requires a re-thinking of the current software stack. To this end, we have undertaken a wide reaching effort at Georgia Tech which evaluates the challenges imposed by the emerging hardware and applications on the entire software stack. We are working on designing and implementing suitable programming models, runtimes, operating system changes and hypervisor changes to prepare software for such future heterogeneous many-core platforms. This effort is a collaboration between different research groups at Georgia Tech and research labs across United States. The project has been split into different components, each addressing a subset of challenges presented by this endeavor. The rest of this page will summarize these efforts and enlist the people involved.

The previous version of this site can be found at http://www.cercs.gatech.edu/projects/HyVM

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